The increasing demand for higher densification and miniaturization impose corresponding demands to produce semiconductor devices with design requirements within the sub-micron range. Various types of lightly doped drain (LDD) transistors having shallow junctions and short channel thresholds have evolved in an attempt to satisfy such demands for miniaturization. A conventional structure having a shallow LDD junction is depicted in FIG. 1 and exhibits favorable short channel threshold and drain induced barrier lowering (DIBL) properties. The conventional structure depicted in FIG. 1 comprises substrate 10 with a shallow p-type doping region 12 extending across the gate and a shallow p-type well 14 beneath the shallow doping region 12. The lateral extent of p-type well 14 is not defined as it extends beyond the locality of the depicted transistor and may serve as a common p-type well for several transistors.
With continued reference to FIG. 1, gate oxide 16 is formed on semiconductor surface 10, and gate polysilicon layer 18 is formed on gate oxide 16. LDD regions 20 are typically formed by ion implantation using the gate electrode as a mask for self-alignment. The extension of LDD regions 20 under gate oxide 16 occurs during subsequent thermal diffusion steps. Heavily doped regions 21 are typically formed by ion implantation masked by gate electrode 18 and sidewall spacer 23 which is typically formed by depositing an oxide layer and anisotropically etching to leave a fillet of material on the sidewalls of polysilicon gate electrode 18. The amount of shallow doping 12 is established by the thickness of the gate oxide 18 to achieve a desired channel threshold. The deeper channel doping region 14 is determined by punch-through considerations.
In U.S. Pat. No. 5,116,778, a method is disclosed for producing a CMOS semiconductor device with a shallow channel. The method disclosed in U.S. Pat. No. 5,212,106 departs from the methodology of U.S. Pat. No. 5,116,778 by forming the source/drain region at a controlled distance spaced apart from the shallow channel implant.
There exists a need for efficient, simplified methodology to produce short channel MOS devices, particularly short channel CMOS devices having sub-micron dimensions with increased drive current, improved short channel characteristics and self-aligned lightly doped source/drain regions.